SRAM (static random access memory) devices are commonly utilized for static memory storage. Each bit is typically stored in an SRAM storage cell with four transistors. Two additional access transistors serve to control access to a storage cell during read and write operations. Access to the cell is enabled by a word line that controls the two access transistors which, in turn, control whether the cell should be connected to the bit lines, which are used to transfer data for both read and write operations.
One of the challenges that must be dealt with in implementing an SRAM is accounting for the delay that occurs between: (1) the time the word line is turned on; and (2) the time the data is ready to be read off of the bit lines with a sensing amplifier. Because the delay can be relatively variable based on any number of factors, some type of circuit for generating a delay is required to notify the sensing amplifier when to fire and read the bit lines. Current approaches utilize logic devices to generate the delay. Unfortunately, logic devices are subject to process, voltage and temperature (PVT) variations that differ from the SRAM cell devices. Using logic devices results in less than optimal performance and increased susceptibility to SRAM cell writability and stability problems.